Stephen Keckler

Dr. Stephen Keckler led his TRIPS (Tera-Op Reliable Intelligently adaptive Processing System) research group in developing an architecture that offers a promising path to scalability without significantly reducing the number of applications that customers can run on their PCs. He completed the science, and the design and engineering required to build a microprocessor, demonstrating the behavior of wires in future technology and the scaling limits of microprocessors. This work identified the distribution of structures as the key issue to be addressed in future designs.

His paper Clock Rate Versus IPC: The End of the Road for Conventional Microarchitectures, which identifies wire delay as a key problem to be faced by future computer designers, is one of the most highly referenced computer architecture papers in recent times. A second paper, Exploiting ILP, DLP, and TLP Using Polymorphism in the TRIPS Processor, addresses grain size in microprocessor architectures and the ability of microprocessors to run applications with different types of parallelism. In addition to describing the characteristics of instruction-level, data-level, and thread-level parallelism, this paper 1) establishes running multiple types of parallelism as a desirable property for future architectures; 2) defines the design space of multiprocessor grain sizes; and 3) provides a set of benchmarks and results that demonstrate the viability of the authors' TRIPS architecture.